Xilinx SDSoC Tool Exploration using AES Encryption
FPGAs provide customizable access to large performance gains from parallelization of software algorithms in programmable logic. However, because FPGA programming is a significant departure from traditional software programming, wide scale utilization of FPGA-based algorithm acceleration has been hindered by a lack of necessary expertise.
The Xilinx SDSoC™ development environment aims to reduce the prerequisite expertise needed to take advantage of FPGA capabilities by facilitating the transition from software algorithm to FPGA hardware logic. This paper presents the methodology and results of accelerating software defined AES-128 CBC and CTR implementations using the Xilinx SDSoC development environment.
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