FPGA development is complex enough when designing systems for use on Earth. But it’s a whole different ballgame when you leave the atmosphere.
The harsh radiation of space can wreak havoc on computer systems and corrupt data. Radiation hardened technology is a must when developing products for space. But these devices present their own brand of technical challenges, the stickiest of which include timing and resets.
Developers need to consider timing penalties when using rad-hard parts. Internal block RAM architecture and error correction features can slow down packets on their way through. Even just a few hundred picoseconds can present significant barriers to successful operation and user experience depending on what the end product is used for.
“If you need speeds above 100 megahertz, some of the rad-hard features can make this challenging,” says DornerWorks FPGA engineer Brian Douglas.
Most developers want to design their FPGA system cleanly and free from inefficient resets. But that’s not always possible. Sometimes processes just don’t all line up to a clock edge. Ordinarily this would warrant an “asynchronous” reset, but rad-hard parts complicate this assumption. The amount of resources available for resets are limited. NASA guidelines further recommend using only asynchronous resets.
“In space and aerospace applications or high reliability applications you want asynchronous resets because you can cause a determined state whenever you need, without waiting for clocks,” Douglas says. “If I/O needs to be turned off, it can be turned off right now.”
In contrast, synchronous resets are generated by memory elements and aligned to a clock. And there’s a good reason they are not preferred in space applications.
“The problem with those resets is that if the clock is not running the reset doesn’t work,” Douglas says. “If you have an issue on a board, say the crystal locks up or the programmable logic-generated clocks have a problem and you can’t really reset the thing, that can be a problem for certain applications.”
So, why not both?
DornerWorks used Microchip’s RTG4 FPGAs in a multi-layer Ethernet networking solution that will improve the quality of life for astronauts in space. The same technology can provide highly reliable data connections between instruments and on-board computers or enable a fleet of remote sensing satellites.
Our engineers implemented a series of “synchronized asynchronous” resets applying them sparingly to reduce inefficient resource utilization.
“It’s a slightly different paradigm than most people are used to,” Douglas says.
There is no direct path from fabric to a reset pin on a memory element within the RTG4 architecture, though register reset pins can technically be reached indirectly using a RGREST. Resets must therefore be promoted to the TMR dedicated reset resources.
This means that resets generated somewhere in the FPGA fabric can get in the way of other processes in the PL.
“There’s obviously a limit,” Douglas says. “If you have multiple asynchronous resets you can end up basically blocking logic from being populated on some rows. Effectively you reduce your resource utilization by doing resets.”
Our system isn’t burdened by these challenges. Douglas and team opted for synchronous resets in the design and implemented them using the Libero software tools.
“There are some IP from Microsemi that use asynchronous resets that are asserted asynchronously but de-asserted synchronously,” Douglas says. “The circuit is essentially asynchronous resets driven by a clocked memory element.”
This is not the type of system that will control safety-critical components like engines or navigational equipment, but it does prove out the flexibility and capability of rad-hard RTG4 FPGAs in the face of harsh radiation.
As a Microchip Authorized Design Partner DornerWorks can help you implement your IP on state-of-the-art RTG4 FPGAs, RT PolarFire FPGAs, the PolarFire SoC and many other hardware solutions from Microchip. Schedule a meeting with us when you are ready to turn your ideas into reality.