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Time Sensitive Networking (TSN) – Deterministic Communication with Time-Aware Shaping

Posted on October 19, 2022 by Richard Chavez

Time-Sensitive Networking (TSN) is a new set of standards that extend the capabilities of the previous set of Audio Video Bridging (AVB) Ethernet network standards, bringing with it several new enhancements which are primarily used to improve performance in highly time-critical scenarios. TSN, such as that of the TSN IP developed by DornerWorks, can be used to facilitate deterministic communication across a network to guarantee that data is sent/received in a very predictable time-frame, avoiding delays due to buffering or congestion in legacy implementations. One of the features of the TSN standards, and the focus of this post, is referred to as “Time-Aware Shaping.”

Richard Chavez is an FPGA engineer for DornerWorks.

Time-Aware Shaping is a method to control which packets of data are sent when at each hop in a network’s data path. The Time-Aware Shaper (TAS) accomplishes this by breaking time down into cycles of user-specified length. These cycles are then further broken down into a user-specified number of time slices within each cycle as shown in Figure 1:

Figure 1: Example of time cycles being divides into time slices
Figure 1: Example of time cycles being divides into time slices

Each of these time slices has a user-specified duration. During each time slice the user configures which priority levels/queues of traffic can be transmitted by specifying which gates (single or multiple gates are possible) corresponding to each queue are “opened” or “closed”, as in Figure 2:

Figure 2: Example of a programmed schedule list to be executed each time cycle, where each traffic queue’s gate is being opened exclusively in a corresponding time slice.
Figure 2: Example of a programmed schedule list to be executed each time cycle, where each traffic queue’s gate is being opened exclusively in a corresponding time slice.

Using this mechanism, time-critical traffic can be sent at very specific, deterministic times without interruptions that could otherwise be caused by congestion from other traffic, as the schedule list can be used to guarantee transmission windows. Further, the TAS can be configured and synchronized at each transmission node across a network. Given that all nodes along the data path are time-synchronized with each other (accomplished using gPTP (802.1AS)), they can be coordinated, and specific packets can be granted a reserved timeframe to propagate across an entire network unimpeded. The user thus has very granular control over which data is sent and when.

The drawback of this system alone is that it is possible for a packet to begin towards the end of a given time slice and thus infringe on the following slice, as in Figure 3:

Figure 3: Packet beginning towards the end of time slice 1 (TS1) infringing on time slice 2.
Figure 3: Packet beginning towards the end of time slice 1 (TS1) infringing on time slice 2.

The TS1 packet would need to complete before TS2 packets could be sent. To resolve this, the TAS can be used with “guard bands” preceding time-critical slices. The guard band is a period (effectively another slice) in between slices during which the corresponding gates are closed such that no new packets from the previous slice can begin, thus “protecting” the next time slice from being infringed upon, as in Figure 4:

Figure 4: A guard band is inserted in between slices, giving time for any packets from the previous slice to fully complete before the next slice begins.
Figure 4: A guard band is inserted in between slices, giving time for any packets from the previous slice to fully complete before the next slice begins.

Using these guard bands, the TAS can then guarantee that the transmission pathway will be free when a time-critical slice arrives. The downside to this, with the TAS by itself, is that the guard bands would need to be sized to equal the duration of a maximum-sized packet (e.g., ~12.3µs for a 1522-B max MTU) to ensure that in a worst-case scenario, if a max-sized packet begins at the very end of the time slice, it has time to finish within the guard band before the next time slice begins. This then has the effects of reduced bandwidth to the network as new data from the previous slice cannot be sent during each of these guard bands, as well as a fixed delay before guaranteed time slices. This is fine for networks where maximum bandwidth is less of a priority and the amount of delay introduced between slices is acceptable but can pose a problem otherwise – particularly in networks where Jumbo packets are used or very minimal latency are required. Fortunately, for such situations, TSN also includes other possible functions to help mitigate this – primarily “Frame Preemption”. Frame preemption adds the ability for packets to be cut off mid-transmission to allow for time-critical packets to be transmitted first. The previous packet can then be resumed afterwards, as seen in Figure 5. Since packets in that case no longer need to complete before another packet can be sent, the guard band duration can be significantly reduced to the size of a maximum preemptable packet fragment instead of an entire packet. The delay between guaranteed slices is minimized and bandwidth is restored as a result:

Figure 5: With Frame Preemption, the TS1 packet can be cut off when time slice 2 arrives, greatly reducing the needed duration of the guard band.
Figure 5: With Frame Preemption, the TS1 packet can be cut off when time slice 2 arrives, greatly reducing the needed duration of the guard band.

Overall, the TAS is a significant addition that comes with the TSN standards and allows for much more control over the timing of packets – something that is proving to be invaluable to a wide range of industries such as aerospace, manufacturing, military, transportation, and many others as networks continue to evolve and reliable, deterministic data arrival grows in importance.

If you would alike to accelerate development of reliably. networked products, contact our team to day and schedule a meeting to turn your ideas into reality!

Richard Chavez
by Richard Chavez
FPGA Engineer
Richard Chavez is an FPGA Engineer at DornerWorks.