On the front lines of battle, every exposed soldier is a potential target, even those behind the turret of a .50 caliber gun.
Placing those soldiers out of harm’s way potentially eliminates their means of fighting back—the job they were sent to do in the first place. Remote weapon operation systems have put them back in the offensive position, but a good offense is nothing without an equally effective defense.
A client in the defense sector came to DornerWorks looking for a reliable video capturing system that could provide the operator with real-time footage from multiple channels using technology that met reduced size, weight, and power (SWaP) requirements.
The goal was complete situational awareness from inside an armored vehicle. Rack-mounted equipment just couldn’t get the job done, and because of specific gaps in knowledge, neither could the client’s in-house engineering team.
DornerWorks understood the client’s need for a powerful and portable solution, and guided them to an FPGA-based Video Processing Unit (VPU) that optimizes situational awareness, allowing an operator access to feeds from seven separate cameras with adjustable points of view and up to 16 configurations, scaled down from HD to NTSC to integrate seamlessly with the remote weapon system.
In the device, an auxiliary processor connected to two analog cameras (NTSC composite video at 640×480) and five HDSDI digital cameras provide the operator functionality to select a single view or tile multiple views to optimize situational awareness. The video inputs are passed through the VPU and fed to the main processing unit (MPU) without modification.
The Video Processing Box is implemented with an Altera Stratix IV GX FPGA to handle all the video stream data. The circuit card is designed to include the following features in addition to the FPGA:
The Video Processing FPGA accepts two BT.656 video streams from analog NTSC decoders and five HD-SDI digital video input streams. It crops, scales and overlays each of the video inputs onto a single mosaic VGA output driving an NTSC encoder. The system utilizes a 64-bit DDR3 memory interface operating at 350MHz for video buffering. It includes a Nios II soft-core processor to handle command, control, and configuration of the FPGA operations, as well.
To ensure a high-quality design, DornerWorks performed numerous signal integrity and FPGA design simulations using the Mentor Graphics toolchain. Mentor’s HyperLynx was used to simulate the high-speed signal paths for signal integrity analysis, and ModelSim was used to verify the high-performance FPGA design prior to integration with the platform circuit card assembly.
The software running on the Nios II soft-core processor operates without an RTOS, and performs the following operations:
Though military spending cuts prevented the client from implementing the Video Processor Unit in a large number of military ground vehicles, the project showed how control, visibility, and safety could be improved on the front lines. Moreover, the manageable size of the finished system means such integration would be both easier and more cost effective.