FPGA Archives - DornerWorks

Make the Most of Rad-Hard RTG4 FPGAs with the Right Approach to Timing and Resets

Posted on January 18, 2021 by Matthew Russell

Tags: FPGA, Microchip, NASA, RTG4, space

Our engineers implemented a series of "synchronized asynchronous" resets on the RTG4s applying them sparingly to reduce inefficient resource utilization....Read more

State-of-the-Art Platforms Provide Opportunity for Innovators and the Senior Engineers Who Guide Them

Posted on September 9, 2020 by Matthew Russell

Tags: FPGA, icicle kit, Intel, Microchip, polarfire, RTG4, SoC, Stratix10, versal, Xilinx

seL4 on PolarFire SOC Provides a Trusted Base for Defense, Industrial and Medical Products

Posted on September 4, 2020 by Matthew Russell

Tags: FPGA, icicle kit, Microchip, microkernel, polarfire, port, seL4, SoC

Four Ways FMCs Can Help You Build Better Products Faster

Posted on August 11, 2020 by Scott Gauche

Tags: DvelopmentKit, FMC, FPGA, hardware, Microchip, MPSoC, SoC, video, Xilinx

Verifying as You Design Using VUnit to Save Time and Improve Accuracy

Posted on August 10, 2020 by Richard Chavez

Tags: Agile, FPGA, modular, test, testbench, testing, verification, VUnit

The Business Potential of Open Source Standards and Tools for FPGA Development

Posted on May 1, 2020 by Matthew Russell

Tags: acap, FPGA, Microchip, opensource, riscv, versal, Xilinx

FPGA Acceleration with Xilinx Versal and the Adaptive Compute Acceleration Platform (ACAP)

Posted on December 3, 2019 by Matthew Russell

Tags: FPGA, MachineLearning, versal, Xilinx

Setting VHDL Generics in FPGA Verification Made Easy with Cocotb

Posted on December 3, 2019 by Juan Morales

Tags: cocotb, FPGA, verification

Install Cocotb on Windows 10 to Boost FPGA Verification Productivity

Posted on December 3, 2019 by Juan Morales

Tags: cocotb, FPGA, verification, walkthrough

Buckle Up! 5 Tips for a Safe FPGA Design

Posted on December 2, 2019 by DornerWorks Ltd.

Tags: design, FPGA, safety

Defeat Obsolescence by Standing Up a Custom IP Microprocessor Core in an UltraScale FPGA

Posted on December 2, 2019 by Eric Hughes

Tags: FPGA, IP, Xilinx, Zynq

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